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For decades, steady advances in traditional planar (meaning two-dimensional) NAND flash have driven dramatic improvements in solid state storage cost, performance, and capacity. As of this week, that train has finally come to an end. Multiple semiconductor manufacturers have announced that they won’t pursue traditional NAND scaling below the 15nm node, and are instead choosing to focus on other ways of improving capacity — specifically, 3D NAND structures.

It’s not surprising to see planar NAND technology take a bow and head for stage left, but the timing is a bit faster than we would’ve guessed. It wasn’t long ago that manufacturers were predicting simultaneous use of 2D and 3D NAND, with 2D NAND pushing to 13nm or below. At the same time, however, the headwinds facing conventional NAND have only been getting stronger. While process node shrinks have generally been viewed as positive for most of the semiconductor industry’s lifetime, node shrinks these days typically have far worse characteristics than their predecessors, at least at first. Instead of relying on the intrinsic properties of smaller wires and lower voltages to automatically boost performance and cut power consumption, semiconductor designers now adopt a number of ancillary technologies and techniques designed to improve the node enough to eke out genuine improvements in both metrics.

3D NAND is expected to push density out dramatically

This is particularly true in NAND flash, where the impact of smaller process nodes means that fewer and fewer electrons are trapped in the cell. This paucity of electrons means that cells are more prone to leaking electrons, thanks to thinner walls, and that they can afford to lose fewer electrons before the gate’s charge falls below the level that can be read as either a 0 or 1. This problem is exacerbated if multiple charge levels are saved per cell (meaning TLC NAND is more affected than MLC, and MLC more than SLC). By shifting to 3D NAND and presumably adopting older nodes, like Samsung has, companies can reap the benefits of die stacking and return to the higher reliability of earlier periods.

A 3D NAND slice.

We suspect that at least some manufacturers will take this road, while others will try to combine their cutting edge planar process technology with die stacking as quickly as possible in order to reap the maximum amount of cost savings and capacity boosts. Intel and Micron are both working on 256Gbit and 384Gbit 3D NAND technology (using MLC and TLC respectively) while Toshiba is working on ramping up its own 48-layer solution.

The good news of this shift is that it should speed further capacity adoption as NAND manufacturers ramp up to higher die stacking techniques. How quickly such benefits will percolate down, however, will depend on how easy it is to migrate to lower process nodes while still using 3D die stacking. When you need to cut 20-40 layers deep into a cell, it’s even harder to make sure everything aligns properly for smaller process nodes. For that reason alone, we don’t expect planar NAND to phase out immediately, and there will likely be a period where 3D and 2D NAND co-exist, with their own cost curves making one or the other a better fit for certain applications.