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As the 3D NAND / V-NAND technology race heats up, multiple companies are racing to demonstrate that they’ve achieved the highest product densities or best overall performance. Samsung may have pioneered the technology in shipping products, but recent statements from Toshiba and Intel gave the impression that the company might be overtaken. Now, Samsung has made its own 3D NAND announcement, and is claiming to be once again in the driver’s seat of the technology.

The company is calling these new RAM chips its third generation of vertical NAND (Samsung tends to refer to its NAND structure as V-NAND rather than 3D NAND, but there’s no functional difference between the two names as far as customers are concerned. This new type of stacks 48-layer chips. It’s only been a year since the Korean company launched its own 32-layer 3-bit V-NAND, which means the company has increased the density of its chips by 50% in just one year. The new 48-layer chips are connected through an estimated 1.8 billion channel holes. A generic diagram of 3D NAND’s structure is shown below:

This may not be exactly what Samsung’s new chips look like, but it works on a conceptual level. The new method of scaling NAND flash isn’t to make individual features or cells smaller, but to stack them in deeper and deeper configurations. Samsung’s new V-NAND contains 85.3 billion cells or 256 billion bits (256Gb). That works out to 32GB per individual IC. Samsung is also claiming that the new 48-layer three-bit NAND is 30% more power efficient than the older 32-layer, 3-bit NAND “when storing the same amount of data.” That implies that the company has made some voltage and power consumption improvements to the drive as well as increasing its density. Samsung also states that the new V-NAND “achieves approximately 40 percent more productivity over its 32-layer predecessor,” but whether this is a reference to yield or to performance isn’t clear from context. Samsung also wants to accelerate the adoption of terabyte-class SSDs, and notes that it intends to increase V-NAND production over the next few months.

3-bit MLC isn’t actually a thing

The one quibble I have with Samsung’s press release is that the company insists on referring to this memory as “3-bit MLC.” Technically, that’s not incorrect, since “MLC” stands for multi-level cell,” not “two.” What terms literally mean and how they’re used don’t always align cleanly, however, and MLC has historically referred to two-bit NAND flash. That’s important, in the tech industry, because storing three bits instead of two inside a flash cell may allow you to hold more data, but it comes with significant trade-offs. TLC NAND is slower than MLC NAND and it has a significantly lower lifetime. After the issues associated with its 840 EVO, Samsung may be trying to dodge a marketing bullet.

At the same time, however, the company does have a point. Samsung currently uses an older 40nm process for its V-NAND, and has previously indicated it will stick with this node for several more product generations. NAND produced on older notes had superior data retention and could endure a higher number of program/erase cycles before failing. By building TLC NAND on 40nm, Samsung has likely obviated some of the issues we saw with conventional 2D NAND around the 20nm node.

This likely puts Samsung’s V-NAND in an awkward spot. It’s going to be better than conventional TLC by virtue of being built on an older process node, but it still won’t have the speed or endurance of two-bit MLC V-NAND. Calling it three-bit MLC, however, obscures the fact that TLC NAND has different performance characteristics than MLC, and it’s an affectation we wish the company would drop.